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Sheet目录320
> DK-DEV-5SGXEA7N (Altera)KIT DEV STRATIX V FPGA 5SGXEA7
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TOC-4
Stratix V Device Handbook Volume 2: Transceivers
Synchronization
State
Machine
Parameters
in
1000BASE-X
and
1000BASE-KX
Configurations..........................................................................................................................4-17
Transceiver
Clocking
in
10GBASE-R,
10GBASE-KR,
1000BASE-X,
and
1000BASE-KX
Configurations..........................................................................................................................4-17
Interlaken....................................................................................................................................................4-17
Transceiver
Datapath
Configuration..........................................................................................4-18
Supported
Features........................................................................................................................4-19
Transceiver
Clocking.....................................................................................................................4-21
PCI
Express
(PCIe)
—
Gen1,
Gen2,
and
Gen3........................................................................................4-23
Transceiver
Datapath
Configuration..........................................................................................4-23
Supported
Features
for
PCIe
Configurations............................................................................4-26
Supported
Features
for
PCIe
Gen3..............................................................................................4-30
Transceiver
Clocking
and
Channel
Placement
Guidelines......................................................4-33
Advanced
Channel
Placement
Guidelines
for
PIPE
Configurations.....................................4-41
Transceiver
Clocking
for
PCIe
Gen3..........................................................................................4-46
XAUI............................................................................................................................................................4-53
Transceiver
Datapath
in
a
XAUI
Configuration.......................................................................4-54
Supported
Features........................................................................................................................4-56
Transceiver
Clocking
and
Channel
Placement
Guidelines......................................................4-59
CPRI
and
OBSAI
—
Deterministic
Latency
Protocols...........................................................................4-60
Transceiver
Datapath
Configuration..........................................................................................4-60
Phase
Compensation
FIFO
in
Register
Mode............................................................................4-62
Channel
PLL
Feedback..................................................................................................................4-62
CPRI
and
OBSAI............................................................................................................................4-62
CPRI
Enhancements......................................................................................................................4-64
Transceiver
Configurations......................................................................................................................4-65
Standard
PCS
Configurations
—
Custom
Datapath...................................................................4-65
Standard
PCS
Configurations
—
Low
Latency
Datapath..........................................................4-71
Transceiver
Channel
Placement
Guidelines..............................................................................4-76
10G
PCS
Configurations...............................................................................................................4-77
Merging
Instances..........................................................................................................................4-84
Native
PHY
IP
Configuration..................................................................................................................4-84
Native
PHY
Transceiver
Datapath
Configuration....................................................................4-85
Standard
PCS
Features..................................................................................................................4-87
10G
PCS
Supported
Features.......................................................................................................4-88
10G
Datapath
Configurations
with
Native
PHY
IP..................................................................4-90
PMA
Direct
Supported
Features..................................................................................................4-93
Channel
and
PCS
Datapath
Dynamic
Switching
Reconfiguration.........................................4-93
Stratix
V
GT
Device
Configurations.......................................................................................................4-93
Altera Corporation
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